Efficient High Speed Compression Trees on Xilinx FPGAs

Compressor trees are efficient circuits to realize multi-operand addition with fast carry-save arithmetic. They can be found in various arithmetic applications like multiplication, squaring and the evaluation of polynomials with application to function approximation. Finding good elementary compressing elements on FPGAs is a non-trivial task as an efficient mapping to look-up tables and carry-chain logic has to be found. It was shown recently that common ternary adders on modern FPGAs outperform previous compressors in terms of area-efficiency, i. e., the number of compressed bits per logic unit. While Altera FPGAs allow a fast and compact implementation of ternary adders we observed that ternary adders on Xilinx FPGAs only achieve about half of the speed of a two-input adder. This work proposes novel compressing elements including different generalized parallel counters and a 4:2 compressor which is based on a modified ternary adder. They provide a better area-efficiency and/or a lower delay than previously proposed compressing elements.